Hardware

Memotech hardware components, and what they included :-

• MTX external PSU.
• MTX motherboard. It had Z80A CPU (at 4MHz), 24KB of ROM, 32KB or 64KB of RAM, VDP chip (TMS 9918 in US, TMS 9929A in Europe) with 16KB of video RAM, a sound chip (TI SN76489A), and a centronics printer port. The ROM could be 8KB+8KB+8KB or 16KB+8KB ROM. The RAM would be 32KB or 64KB. So there are 4 permutations, and I have the PALASM for each. Interestingly, we can see from this what happens in RELCPMH=1 mode when you only have 32KB RAM (the manual doesn't show this). Picture.
• MTX memory upgrade. Had 32KB of extra RAM. Sat inside the MTX500 case, on the right. Picture.
• MTX serial card. Connected to the right hand side of the MTX motherboard. It had Z80 DART and two RS232 serial ports. Picture.
• MTX RAM card, typically containing 512KB RAM. Could contain lesser amounts, although I never saw this. This would either be available to MTX BASIC, or could be made to appear as RAM disc to CP/M (as drive F: type 51).
• MTX ROM card, with 4 slots for "2764" 8KB EPROMs. Had connector on both sides, but typically connected to the right hand side of the MTX motherboard. Someone else has reported connecting ROM cards to the left. Writing a byte to 0x0000-0x1fff when in RELCPMH=0 mode selects the sub-page (0x00-0x03), which selects which of the 4 8KB ROM appears in ROM page 2. I have the PALASM for the PAL used on this card. Picture.
• FDX 80 column card, producing output for a monitor, rather than a TV.
• Combined MTX serial card and 80 column card
• FDX disc controller card. Known as SJM's (=Steve Marchant) floppy controller. It had a WD1791 disk controller chip supporting 4 disk drives. Supported 5.25" and 8" disk drives. Reported to not be able to drive 3.5" disk drives (although I think I did once have a 3.5" drive hooked up to my FDX).
• FDX Silicon disc. Various memory sizes were available. This was basically memory accessible through I/O ports, which appeared as discs to CP/M. Expensive, but fast.
• SDX floppy disc controller card, earlier version. Known as TB's (=Tony Brewer?) floppy controller. Had a relatively thin circuit board. It had a WD disk controller chip supporting 2 disk drives Connected to the left hand side of the MTX motherboard. Connected to one or two external drives, which were typically type 03 5.25", but could be type 03 3.5". Had an 8KB SDX ROM (supporting 2x type 03 drives), in ROM slot 3. Picture.
• SDX floppy disc controller card, later version. Also known as TB's (=Tony Brewer?) floppy controller. Had a wider circuit board (as wide as a 3.5" disk drive). Had a single 3.5" type 07 disk. Only capable of driving a single disk (per hardware investigation below). Had a 16KB containing a 8KB CP/M boot ROM (80 column or SCPM variant) in ROM slot 4, and the 8KB SDX ROM (supposedly supporting 2x type 07 drives, but see SDX ROM investigation below), in ROM slot 5. Had sockets for 512KB of RAM, often populated, which was used as 512KB type 51 RAM Disc. Picture,

Download scans of the hardware related pages from the first and second revisions of the "Memotech MTX Series Basic Tutor, Reference & Operators Manual". Includes full circuit diagrams and PALASM.

Memory investigation

Earlier MTX motherboards had 3 x 8KB ROMs. Later ones had a 16KB ROM and an 8KB ROM. Or possibly 2 16KB ROMs in which 8KB wasn't used in one of them (its hard to tell looking at it).

An MTX500 used 8 x 4132 DRAM chips (or similar, eg: my MTX500 uses M3732L-20RS). An MTX512 used 8 x 4164 DRAM chips (or similar). I believe an MTX500 could support certain "half-working" 4164 chips, so seeing these chips on a motherboard doesn't in itself imply 64KB RAM.

Therefore there are 4 permutations of ROM and RAM configuration, and as both ROM and RAM decode is handled by a single PAL14L4 PAL socketed at position A6 on the motherboard, there are 4 PALASM definition files. The PALASM for these are included in the second manual, and scans of these are included in the download earlier on this page. The PALASM snippets that are quoted below are the same logic, with white space added and terms reordered for readability.

There is a hardwired 6-pin link-block at position B7 on the motherboard. It controls the passthrough of NA15 and A14 into the RAS/CAS address multiplexing which feeds the DRAMs. On an MTX512, I believe C should be wired to 4 and R should be wired to 2, thus ensuring both NA15 and A15 are passed through. On my MTX500, C is wired to L, ensuring that NA15 is always 0. I think the link block is done this way so that the MTX500 could use half-working 4164s. This particular setup supports the case where the bottom 32k of the 4164s worked, but I'm sure different link-block configurations would allow the case where the top 32k worked, or the first and third quarters, or second and fourth quarters.

There is another hard-wired link just above the PAL at position A6, known as LK7, and this signal referred to in the PALASM as I2H4L. In the MTX512 I believe this would be wired to 4, ie: low. On my MTX500 it is wired to 2, ie: high. I think this link is a test feature.

The PALASM for a system with 3 x 8KB ROM includes this :-

/CEA  = /RELCPMH                   * /A15 * /A14 * /A13 * /MREQL * /RDL
/CE64 = /RELCPMH * /R2 * /R1       * /A15 * /A14 * /A13 * /MREQL * /RDL
      + /RELCPMH *  R2 *  R1 *  R0 * /A15 * /A14 * /A13 * /MREQL * /RDL 

CEA recognises the fixed ROM.

CE64 recognises ROM pages 0, 1 or 7. CE64 is further decoded outside the PAL to distinguish between ROM pages 0 and 1, and ROM page 7, known as the "games ROM".

The PALASM for a system with 16KB + 8KB ROM includes this instead :-

/CEA  = /RELCPMH                   * /A15 * /A14 * /A13 * /MREQL * /RDL
      + /RELCPMH * /R2 * /R1 * /R0 * /A15 * /A14 *  A13 * /MREQL * /RDL
/CE64 = /RELCPMH * /R2 * /R1 *  R0 * /A15 * /A14 *  A13 * /MREQL * /RDL
      + /RELCPMH *  R2 *  R1 *  R0 * /A15 * /A14 *  A13 * /MREQL * /RDL

CEA recognises the fixed ROM and ROM page 0.

CE64 recognises ROM pages 1 and 7. CE64 is further decoded outside the PAL.

The PALASM for a system with 32KB RAM includes this :-

/NA15 =                                    /A15
      + /RELCPMH * /P3 * /P2 * /P1 *  P0 *  A15 * /A14 * /MREQL
/RAM  =                                     A15 *  A14 * /MREQL
      +            /P3 * /P2 * /P1 * /P0 *  A15 * /A14 * /MREQL
      +  RELCPMH * /P3 * /P2 * /P1 * /P0        * /A14 * /MREQL * /I2H4L
      + /RELCPMH * /P3 * /P2 * /P1 *  P0 *  A15 * /A14 * /MREQL * /I2H4L

NA15 is used to map references to 0x8000-0xbfff in RAM page 1 to references to 0x0000-0x3fff in the DRAM. This only provides any value if I2H4L is set differently.

RAM is used to decide when RAM is visible. The first term covers the top 0xc000-0xfff, visible in both RELCPMH modes, visible in all RAM pages. The second term covers 0x8000-0xbfff in both RELCPMH modes, in RAM page 0. The last two terms make the lower 16KB of RAM visible in other places, but only if the I2H4L wires are set differently (for testing?).

The PALASM for a system with 64KB RAM includes this :-

/NA15 =                                    /A15
      + /RELCPMH * /P3 * /P2 * /P1 *  P0 *  A15 * /A14 * /MREQL
/RAM  =                                     A15 *  A14 * /MREQL
      +  RELCPMH * /P3 * /P2 * /P1 * /P0               * /MREQL * /I2H4L
      + /RELCPMH * /P3 * /P2 * /P1 * /P0 * /A15 *  A14 * /MREQL * /I2H4L
      + /RELCPMH * /P3 * /P2 * /P1       *  A15 * /A14 * /MREQL * /I2H4L

NA15 is used to map references to 0x8000-0xbfff in RAM page 1 to references to 0x0000-0x3fff in the DRAM.

Looking at RAM: The first term covers the top 0xc000-0xfff, visible in both RELCPMH modes, visible in all RAM pages. The second term covers all the RAM in RELCPMH=1 mode, in RAM page 0. The third term covers 0x4000-0x7fff in RELCPMH=0 mode, in RAM page 0. The fourth term covers 0x8000-0xbfff in RELCPMH=0 mode, in RAM pages 0 and 1. Note that we need I2H4L to be low for the full MTX512 memory map to be implemented, therefore I believe this link is wired the opposite way on an MTX512 to how it is on a MTX500. Again, I think the I2H4L link is a test feature, which when invoked makes all but the top 16KB of RAM disappear.

Upgrading MTX500 to MTX512

Recommended procedure (untested as yet) :-

1. Check system works as an MTX500
2. Desolder and remove 8 x 4132
3. Solder in 8 x 16 pin DIL sockets
4. Insert 8 x 4164
5. Check system still works as an MTX500
6. Blow new PAL14L4 and replace existing PAL
7. In the 6-pin link-block snip link between C and L, and make a new link between C and 4
8. Check system works as MTX512. eg: PRINT PEEK(64122) should now return 1, rather than 0.

Note, the above procedure does not suggest breaking and remaking the I2H4L link, close to the PAL chip at A6 on the motherboard. Instead, I suggest you use PALASM for 64KB RAM that simply does not reference the I2H4L input. One less thing to mess up soldering.

Futurlec might be a good place to pick up the parts, as they list the DRAMs, Sockets and PALs referred to above.

SDX hardware investigation

The expectation is that is will be possible to use this same source and driver code if I actually build REMEMOrizer.

Here are the scans of the SDX ROM listing, scanned with what looks like black and white and grayscale settings. Most of the text can be deduced looking at (one or more of) these.