Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.1 (WebPack) - P.15xf Target Family: Spartan3E
OS Platform: LIN Target Device: xc3s500e
Project ID (random number) 14b5779315c54374b6f26a283fcfe455.1F4892AB4D90E27DCD1BFAB54E8B6BAA.13 Target Package: vq100
Registration ID 210642203_0_0_919 Target Speed: -4
Date Generated 2012-11-14T19:06:45 Tool Flow ISE
 
User Environment
OS Name Fedora OS Release Fedora release 14 (Laughlin) ERROR: ld.so: object '/opt/Xilinx/14.1/ISE_DS/ISE/lib/lin/libstdc++.so' from LD_PRELOAD cannot be preloaded: ignored. ERROR: ld.so: object '/opt/Xilinx/14.1/ISE_DS/ISE/lib/lin/libTw.so' from LD_PRELOAD cannot be preloaded: ignored.
CPU Name Intel(R) Core(TM)2 CPU 6600 @ 2.40GHz CPU Speed 2394.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=21
  • 10-bit adder=3
  • 14-bit adder=1
  • 3-bit adder=1
  • 4-bit adder=2
  • 5-bit adder=3
  • 6-bit adder=1
  • 8-bit adder=1
  • 8-bit subtractor=9
Comparators=9
  • 3-bit comparator greatequal=3
  • 9-bit comparator greatequal=3
  • 9-bit comparator less=3
Counters=1
  • 12-bit up counter=1
Multiplexers=33
  • 1-bit 4-to-1 multiplexer=32
  • 8-bit 4-to-1 multiplexer=1
Multipliers=1
  • 5x6-bit registered multiplier=1
Priority Encoders=32
  • 1-bit 1-of-6 priority encoder=32
RAMs=1
  • 16384x8-bit dual-port block RAM=1
ROMs=2
  • 128x3-bit ROM=2
Registers=445
  • Flip-Flops=445
MiscellaneousStatistics
  • AGG_BONDED_IO=66
  • AGG_IO=66
  • AGG_SLICE=896
  • NUM_4_INPUT_LUT=1618
  • NUM_BONDED_IBUF=24
  • NUM_BONDED_IOB=42
  • NUM_BUFGMUX=2
  • NUM_CYMUX=58
  • NUM_LUT_RT=48
  • NUM_MULT18X18SIO=1
  • NUM_RAMB16=8
  • NUM_SLICEL=896
  • NUM_SLICE_FF=446
  • NUM_XOR=64
NetStatistics
  • NumNets_Active=1784
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=224
  • NumNodesOfType_Active_BRAMDUMMY=48
  • NumNodesOfType_Active_CLKPIN=333
  • NumNodesOfType_Active_CNTRLPIN=314
  • NumNodesOfType_Active_DOUBLE=4956
  • NumNodesOfType_Active_DUMMY=5737
  • NumNodesOfType_Active_DUMMYBANK=150
  • NumNodesOfType_Active_DUMMYESC=16
  • NumNodesOfType_Active_GLOBAL=142
  • NumNodesOfType_Active_HFULLHEX=29
  • NumNodesOfType_Active_HLONG=5
  • NumNodesOfType_Active_HUNIHEX=265
  • NumNodesOfType_Active_INPUT=6270
  • NumNodesOfType_Active_IOBOUTPUT=16
  • NumNodesOfType_Active_OMUX=1542
  • NumNodesOfType_Active_OUTPUT=1660
  • NumNodesOfType_Active_PREBXBY=1528
  • NumNodesOfType_Active_VFULLHEX=186
  • NumNodesOfType_Active_VLONG=34
  • NumNodesOfType_Active_VUNIHEX=466
  • NumNodesOfType_Gnd_BRAMDUMMY=58
  • NumNodesOfType_Gnd_DOUBLE=28
  • NumNodesOfType_Gnd_DUMMYBANK=2
  • NumNodesOfType_Gnd_INPUT=76
  • NumNodesOfType_Gnd_OMUX=30
  • NumNodesOfType_Gnd_OUTPUT=20
  • NumNodesOfType_Gnd_PREBXBY=7
  • NumNodesOfType_Gnd_VFULLHEX=2
  • NumNodesOfType_Vcc_BRAMDUMMY=18
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=34
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=23
SiteStatistics
  • IBUF-DIFFM=8
  • IBUF-DIFFMI=2
  • IBUF-DIFFS=8
  • IBUF-DIFFSI=3
  • IBUF-IOB=1
  • IOB-DIFFM=20
  • IOB-DIFFS=20
  • SLICEL-SLICEM=444
SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • IBUF=24
  • IBUF_INBUF=24
  • IBUF_PAD=24
  • IOB=42
  • IOB_INBUF=8
  • IOB_OUTBUF=42
  • IOB_PAD=42
  • MULT18X18SIO=1
  • MULT18X18SIO_MULT18X18SIO=1
  • RAMB16=8
  • RAMB16_RAMB16=8
  • RAMB16_RAMB16A=8
  • RAMB16_RAMB16B=8
  • SLICEL=896
  • SLICEL_C1VDD=4
  • SLICEL_CYMUXF=32
  • SLICEL_CYMUXG=26
  • SLICEL_F=820
  • SLICEL_F5MUX=105
  • SLICEL_FFX=265
  • SLICEL_FFY=181
  • SLICEL_G=798
  • SLICEL_GNDF=21
  • SLICEL_GNDG=20
  • SLICEL_XORF=32
  • SLICEL_XORG=32
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS33:24]
  • PULL=[PULLUP:21]
IOB
  • O1=[O1_INV:0] [O1:42]
  • T1=[T1_INV:0] [T1:8]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:42]
  • TRI=[TRI_INV:0] [TRI:8]
IOB_PAD
  • DRIVEATTRBOX=[12:36] [16:6]
  • IOATTRBOX=[LVCMOS33:42]
  • SLEW=[SLOW:42]
MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:1]
  • CEB=[CEB_INV:0] [CEB:1]
  • CEP=[CEP:1] [CEP_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:1]
MULT18X18SIO_MULT18X18SIO
  • AREG=[1:1]
  • BREG=[0:1]
  • B_INPUT=[DIRECT:1]
  • CEA=[CEA_INV:0] [CEA:1]
  • CEB=[CEB_INV:0] [CEB:1]
  • CEP=[CEP:1] [CEP_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • PREG=[0:1]
  • PREG_CLKINVERSION=[0:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:1]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA=[WEA:8] [WEA_INV:0]
  • WEB=[WEB:8] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • PORTA_ATTR=[16384X1:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • WEA=[WEA:8] [WEA_INV:0]
  • WRITEMODEA=[READ_FIRST:8]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • PORTB_ATTR=[16384X1:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEB=[WEB:8] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:8]
SLICEL
  • BX=[BX_INV:0] [BX:155]
  • BY=[BY:73] [BY_INV:0]
  • CE=[CE:268] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:26]
  • CLK=[CLK:316] [CLK_INV:0]
  • SR=[SR:20] [SR_INV:18]
SLICEL_CYMUXF
  • 0=[0:32] [0_INV:0]
  • 1=[1_INV:0] [1:32]
SLICEL_CYMUXG
  • 0=[0:26] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:105] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:6] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:229] [CE_INV:0]
  • CK=[CK:265] [CK_INV:0]
  • D=[D:265] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:259] [INIT1:6]
  • FFX_SR_ATTR=[SRLOW:263] [SRHIGH:2]
  • LATCH_OR_FF=[FF:265]
  • REV=[REV_INV:0] [REV:2]
  • SR=[SR:13] [SR_INV:17]
  • SYNC_ATTR=[ASYNC:235] [SYNC:30]
SLICEL_FFY
  • CE=[CE:159] [CE_INV:0]
  • CK=[CK:181] [CK_INV:0]
  • D=[D:181] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:176] [INIT1:5]
  • FFY_SR_ATTR=[SRLOW:180] [SRHIGH:1]
  • LATCH_OR_FF=[FF:181]
  • REV=[REV_INV:0] [REV:4]
  • SR=[SR:18] [SR_INV:1]
  • SYNC_ATTR=[ASYNC:162] [SYNC:19]
SLICEL_XORF
  • 1=[1_INV:0] [1:32]
SLICEM
  • BX=[BX_INV:0] [BX:4]
  • BY=[BY:4] [BY_INV:0]
SLICEM_F
  • LUT_OR_MEM=[LUT:2]
SLICEM_F5MUX
  • S0=[S0:4] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:4] [S0_INV:0]
SLICEM_G
  • LUT_OR_MEM=[LUT:4]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
IBUF
  • I=24
  • PAD=24
IBUF_INBUF
  • IN=24
  • OUT=24
IBUF_PAD
  • PAD=24
IOB
  • I=8
  • O1=42
  • PAD=42
  • T1=8
IOB_INBUF
  • IN=8
  • OUT=8
IOB_OUTBUF
  • IN=42
  • OUT=42
  • TRI=8
IOB_PAD
  • PAD=42
MULT18X18SIO
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • CEA=1
  • CEB=1
  • CEP=1
  • CLK=1
  • P0=1
  • P1=1
  • P2=1
  • P3=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
  • RSTA=1
  • RSTB=1
  • RSTP=1
MULT18X18SIO_MULT18X18SIO
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • CEA=1
  • CEB=1
  • CEP=1
  • CLK=1
  • P0=1
  • P1=1
  • P2=1
  • P3=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
  • RSTA=1
  • RSTB=1
  • RSTP=1
RAMB16
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB0=8
  • ADDRB1=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIA0=8
  • DOA0=8
  • DOB0=8
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA=8
  • WEB=8
RAMB16_RAMB16
  • ADDRA=8
  • ADDRB=8
  • DIA=8
  • DIB=8
  • DOA=8
  • DOB=8
RAMB16_RAMB16A
  • ADDRA=8
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • CLKA=8
  • DIA=8
  • DIA0=8
  • DOA=8
  • DOA0=8
  • ENA=8
  • SSRA=8
  • WEA=8
RAMB16_RAMB16B
  • ADDRB=8
  • ADDRB0=8
  • ADDRB1=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKB=8
  • DIB=8
  • DOB=8
  • DOB0=8
  • ENB=8
  • SSRB=8
  • WEB=8
SLICEL
  • BX=155
  • BY=73
  • CE=268
  • CIN=26
  • CLK=316
  • COUT=26
  • F1=819
  • F2=791
  • F3=757
  • F4=541
  • G1=793
  • G2=768
  • G3=723
  • G4=542
  • SR=38
  • X=602
  • XQ=265
  • Y=584
  • YQ=181
SLICEL_C1VDD
  • 1=4
SLICEL_CYMUXF
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
SLICEL_CYMUXG
  • 0=26
  • 1=26
  • OUT=26
  • S0=26
SLICEL_F
  • A1=819
  • A2=791
  • A3=757
  • A4=541
  • D=820
SLICEL_F5MUX
  • F=105
  • G=105
  • OUT=105
  • S0=105
SLICEL_F6MUX
  • 0=6
  • 1=6
  • OUT=6
  • S0=6
SLICEL_FFX
  • CE=229
  • CK=265
  • D=265
  • Q=265
  • REV=2
  • SR=30
SLICEL_FFY
  • CE=159
  • CK=181
  • D=181
  • Q=181
  • REV=4
  • SR=19
SLICEL_G
  • A1=793
  • A2=768
  • A3=723
  • A4=542
  • D=798
SLICEL_GNDF
  • 0=21
SLICEL_GNDG
  • 0=20
SLICEL_XORF
  • 0=32
  • 1=32
  • O=32
SLICEL_XORG
  • 0=32
  • 1=32
  • O=32
SLICEM
  • BX=4
  • BY=4
  • F5=4
  • FX=2
  • FXINA=4
  • FXINB=4
  • G1=2
  • G2=2
  • G3=2
  • G4=2
  • Y=2
SLICEM_F
  • D=2
SLICEM_F5MUX
  • F=2
  • G=4
  • OUT=4
  • S0=4
SLICEM_F6MUX
  • 0=4
  • 1=4
  • OUT=4
  • S0=4
SLICEM_G
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • D=4
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 22 21 0 0 0 0 0
bitgen 102 102 0 0 0 0 0
map 107 107 0 0 0 0 0
ngc2edif 4 4 0 0 0 0 0
ngdbuild 116 116 0 0 0 0 0
par 106 103 2 0 0 0 0
trce 102 102 0 0 0 0 0
xst 231 207 0 0 0 0 0
 
Help Statistics
Unsuccessful Search words
is never assigned ( 1 ) never assigned ( 1 )
Help files
/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm ( 1 ) /doc/usenglish/isehelp/ise_c_fpga_design_flow_overview.htm ( 1 )
/doc/usenglish/isehelp/ise_c_setting_custom_compile_order.htm ( 1 ) /doc/usenglish/isehelp/ise_c_using_xst_for_synthesis.htm ( 2 )
/doc/usenglish/isehelp/ise_c_xst_area_reduction_strategies.htm ( 1 ) /doc/usenglish/isehelp/ise_c_xst_performance_strategies.htm ( 1 )
/doc/usenglish/isehelp/ise_c_xst_power_reduction_strategies.htm ( 1 ) /doc/usenglish/isehelp/ise_p_using_synplify_for_synthesis.htm ( 1 )
/doc/usenglish/isehelp/ise_p_viewing_a_technology_schematic_syn.htm ( 1 ) /doc/usenglish/isehelp/ise_p_viewing_a_technology_schematic_xst.htm ( 1 )
/doc/usenglish/isehelp/pp_db_xst_synthesis_options.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_ProjectDescription=TMS9918A replacement PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-10-28T14:04:30
PROP_intWbtProjectID=1F4892AB4D90E27DCD1BFAB54E8B6BAA PROP_intWbtProjectIteration=13
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_xstNetlistHierarchy=Rebuilt
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=vq100 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=7
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=23 NGDBUILD_NUM_FDE=374
NGDBUILD_NUM_FDR=27 NGDBUILD_NUM_FDRE=13 NGDBUILD_NUM_FDRS=6 NGDBUILD_NUM_FDS=2
NGDBUILD_NUM_FDSE=1 NGDBUILD_NUM_GND=3 NGDBUILD_NUM_IBUF=7 NGDBUILD_NUM_INV=6
NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT1=45 NGDBUILD_NUM_LUT2=60 NGDBUILD_NUM_LUT2_D=13
NGDBUILD_NUM_LUT2_L=6 NGDBUILD_NUM_LUT3=340 NGDBUILD_NUM_LUT3_D=43 NGDBUILD_NUM_LUT3_L=13
NGDBUILD_NUM_LUT4=849 NGDBUILD_NUM_LUT4_D=89 NGDBUILD_NUM_LUT4_L=146 NGDBUILD_NUM_MULT18X18SIO=1
NGDBUILD_NUM_MUXCY=58 NGDBUILD_NUM_MUXF5=105 NGDBUILD_NUM_OBUF=34 NGDBUILD_NUM_RAMB16_S1_S1=8
NGDBUILD_NUM_VCC=4 NGDBUILD_NUM_XORCY=64
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=23 NGDBUILD_NUM_FDE=374 NGDBUILD_NUM_FDR=27
NGDBUILD_NUM_FDRE=13 NGDBUILD_NUM_FDRS=6 NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=3 NGDBUILD_NUM_IBUF=31 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=6
NGDBUILD_NUM_LUT1=45 NGDBUILD_NUM_LUT2=60 NGDBUILD_NUM_LUT2_D=13 NGDBUILD_NUM_LUT2_L=6
NGDBUILD_NUM_LUT3=340 NGDBUILD_NUM_LUT3_D=43 NGDBUILD_NUM_LUT3_L=13 NGDBUILD_NUM_LUT4=849
NGDBUILD_NUM_LUT4_D=89 NGDBUILD_NUM_LUT4_L=146 NGDBUILD_NUM_MULT18X18SIO=1 NGDBUILD_NUM_MUXCY=58
NGDBUILD_NUM_MUXF5=105 NGDBUILD_NUM_OBUF=34 NGDBUILD_NUM_OBUFT=8 NGDBUILD_NUM_PULLUP=31
NGDBUILD_NUM_RAMB16_S1_S1=8 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=4 NGDBUILD_NUM_XORCY=64
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-vq100 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=Rebuilt -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5